1. Field of the Invention
This invention relates to a half-sized Peripheral Component Interconnect (hereinafter abbreviated as PCI) CPU card and a computer device, more particularly to a half-sized PCI CPU card and a computer device having PCIe expansion capability for utilizing the hot pull-plug and high transmission properties of the PCIe bus and communicating with a PCIe bus compatible peripheral inserted into a back plane of the computer device.
2. Description of Related Art
Conventionally, Peripheral Component Interconnect (hereinafter abbreviated as PCI) is a bus standard used as an interface between a motherboard and a peripheral device. Generally speaking, devices compatible with the PCI standard can be categorized into the following two different types according to the ways connecting with the motherboard:                (1) as an integrated circuit (IC) directly installed on the motherboard, which is named as “planar device” in the PCI standard; and        (2) as an interface card inserted into a slot of the motherboard and having the feature of plug and play.        
The PCI bus standard was developed by Intel in year 1990s. On Jun. 22, 1992, Intel announced PCI 1.0 standard that was a standard applying to components. Then, on Apr. 30, 1993, PCI-SIG announced PCI 2.0 standard that was a standard between the connector and the motherboard slot for the first time. Then, PCI standard was soon applied to a server for replacing the original MCA and EISA, and thus became the only one bus expansion provided in the server. In a mainstream personal computer, PCI standard gradually replaced a VESA local bus (VLB). Until the end of 1994, after a second generation of Pentium computer was introduced, PCI standard won significant breakthrough in the market. In year 1996, VLB thoroughly exited from the PC market, and manufacturers even applied the PCI to a 476 computer. Although EISA thereafter worked with PCI until 2000, the subsequent versions of PCIs were continuously upgraded for promotion of their performance. Until year 2004, Intel introduced PCI Express as a serial bus, motherboard manufacturers gradually got rid of the conventional PCI slot and introduced the PCI Express interface.
PCI Express (hereinafter abbreviated as PCIe) is a type of PCI bus, being used for the existing PCI programming concept and communication standard and provided with a faster serial communication system. Generally speaking, PCIe is used for internal interconnection only. Since the PCIe bus is provided on the basis of the existing PCI bus, it only needs to modify the physical layer of the existing PCI bus, but not the software, while converting the existing PCI bus into the PCIe bus. Further, the transmission rate of PCIe bus is higher, so the PCIe bus may be used to replace almost all of the existing internal bus, including AGP and PCI. Intel even hoped to use a PCIe bus controller to communicate with all of the external devices for data transmission so as to replace an existing South Bridge or North Bridge chip.
Even, the PCIe bus was designed mainly for raising the transmission rate of all the buses installed in a computer, so there are many different standards in bandwidth; for example, PCIex16 is a standard dedicated to a display card. Compared with the PCI bus, in the aspect of connection, the PCIe bus is provided on a transmission channel based on a two-sided point-to-point connection, in which different transmission channels are used to transmit and receive different data and four sets of data may be implemented in each channel. Thus, the connection between the two PCIe devices becomes a linkage, forming one or more transmission channels; namely, the linkage where each device supports at least one transmission channel (x1) may also be a linkage for 2, 4, 7, 16, or 32 transmission channel, thereby better bi-directional compatibility being achieved. On the contrary, PCI is connected under control of the bus, and thus all the devices are made to share a unidirectional 32-bit parallel bus.
Conventionally, a backplane is provided on an industrial computer or a server, as shown in FIG. 1. The backplane 10 is a printed circuit board on which a plurality of insertion slots 11 are arranged in parallel, in which each pin is electrically connected to each other through the wiring 12 arranged on the backplane 10. Generally speaking, the requirements of pin in each insertion slot 11, such as size and amount, must meet the bus standard connected to the motherboard and the external device(s), such as that of Peripheral Component Interconnect (PCI) bus. Thus, depending on actual requirements, a user may insert a CPU card following the standard of PCI bus into each of the insertion slots 11. In the following description of this invention, the CPU card following PCI bus standard is briefly named PCI CPU Card.
Generally speaking, the CPU card is equal to a computer, and upon requests is provided with all interfaces required for normal operation of the computer, such as a VGA component and interface for video control, COM1 and COM2 components and interfaces for communication control, a LPT component and interface for printer control, a Floppy drive control component and interface, an AUDIO component and interface for audio control, a DVD signal I/O interface, a LCD control component and interface, a USB transmission interface and the like. With reference to FIG. 2, the CPU card 20 is mainly made up with a CPU 21, a North Bridge chip 22, and a South Bridge chip 23, in which the North Bridge chip 22 is connected to the CPU 21 and the South Bridge chip 23, and is provided to connect a memory and a video card (not shown) to transmit signals at a high speed among the CPU 21, the memory, and the video card and make the CPU 21 and the South Bridge chip 23 communicate with each other; the South Bridge chip 23 connects a PCI Bus 24, Real Time Clock (not shown), Power Management (not shown), a USB transmission interface (not shown), and other devices to transmit signals at a low speed and make the CPU 21 and the golden finger 25 of PCI bus 24 communicate with each other through the North Bridge chip 22 and the CPU 21 that contact with each other.
In recent years, the PCIe bus being featured with pull and plug, heat exchange, and high transmission efficiency gradually replaces the PCI bus and is applied to various South Bridge chips and peripherals. Thus, manufacturers of the South Bridge chip added a PCIe bus compatible interface design to a newly introduced South Bridge chip, serving as an expansion bus for the South Bridge chip to connect with other high-speed PCIe bus compatible peripherals. However, the size of a conventional half-sized PCI CPU card widely used in the IPC or the server is limited to a specified range. Although the new South Bridge chip compatible to the PCIe bus is used in the half-sized PCI CPU card, due to the limited size, any expansion slot cannot be added to the half-sized PCI CPU card. Thus, the PCIe bus compatible expansion slot is not designed in the conventional half-sized PCI CPU card and its backplane so that the high-speed PCIe bus compatible peripherals (hereinafter abbreviated as PCIe peripherals) cannot be expanded in the half-sized PCI CPU card. Thus, what the manufacturers make great effort to earnestly improve is making the PCIe peripherals to be expandable through the conventional half-sized PCI CPU card and its backplane in the IPC or the server for effective promotion of the efficiency of transmission and operation.
Consequently, because of the technical defects of described above, the applicant keeps on carving unflaggingly through wholehearted experience and research to develop the present invention, which can effectively improve the defects described above.